Recently, new circuits have been developed to implement both CMOS and bipolar devices on the same semiconductor chip to benefit from their respective advantages, leading to what is known as BiCMOS technologies. For instance, more and more Static Random Access Memories (SRAMs) designs use these BiCMOS technologies to achieve better speeds than pure CMOS memories and lower power consumptions than pure bipolar memories. As a result, both bipolar devices (such as of the ECL type) and CMOS devices are simultaneously found in the same chip. A major concern with BiCMOS circuits, however, is that the high and low voltage levels in ECL circuits are different than those in CMOS circuits. For example, typical ECL circuits operate with standard high and low voltages of approximately -0.9 and -1.7 volts respectively, while typical CMOS circuits operate with high and low voltages of about -0.4 and 4.1 volts respectively. As a result, in order to couple the output of an ECL circuit to the input of a CMOS circuit, a converting circuit is commonly employed to change the logic levels. For example, most of the BiCMOS stand-alone SRAM chips require input buffers or receivers with ECL compatible input voltages and CMOS compatible output voltages. As a matter of fact, input buffers are essential to the overall performance of BiCMOS SRAMs chips. In addition, high density BiCMOS SRAMs (1Mb to 4Mb and over) require CMOS transistors with submicronic gate lengths that often cannot withstand ECL power supply levels. For example, in the ECL 100 K family, the standard supply voltages that are applied are Vee=-4.5 V and Vcc=0 V. These supply voltages, however, produce a "hot electron effect" in CMOS circuits which thereby causes undesirable threshold voltage (VT) shifts. For all these reasons, it is required to supply dense BiCMOS SRAMs with power supplies that provide supply voltages lower than those used for the bipolar circuits.
A typical state of the art input buffer consists of three stages: an ECL receiver, an ECL-CMOS level-shifter, and an output driver. Unfortunately, with this conventional type of circuit, current flows constantly therein, thereby causing permanent power dissipation. Another problem is that ECL voltages tend to drift with changes in environmental conditions such as temperature. Because the swing between the high and low levels for an ECL circuit is only 0.8 volts, changes of a few tenths of a volt can create performance and noise margin problems that are detrimental to correct operation of the circuit.
Still another problem is that the level conversion produced by the level-shifter stage introduces a propagation delay which adversely affects the performance of the input buffer. The number of transistors used in the level-shifter stage has a direct impact on the performance and on chip space required to implement the input buffer in an integrated circuit.
A recent tentative solution of the prior art to these acute problems is given in: an article "An 8 ns 256 k BiCMOS RAM", by Tamba et al, published in the IEEE Journal of Solid State Circuits, Aug. 1989, pp.1021-1026 (Ref. (1). According to this article, and more particularly in FIG. 8 thereof, there is disclosed a two-stage input buffer that converts input signals of the ECL standard into output signals of the CMOS type. For sake of illustration, this two-stage input buffer is represented in FIG. 1 of the present patent application where it bears reference 10.
Referring now to FIG. 1, the first stage 11 of input buffer 10 is formed by an input emitter-follower circuit 12, a current-switch circuit 13, and an active pull-down circuit 14. The input emitter-follower circuit 12 comprises NPN transistor Q1 and current source I.sub.o. The current-switch circuit 13 is formed by NPN transistors Q2 and Q3 connected in a differential configuration and fed by current source I1 (Q4/R3). NPN transistors Q2 and Q3 are respectively loaded by resistors R1 and R2. The base of transistor Q2 is driven by the emitter of transistor Q1, while the base of transistor Q3 is connected to a reference voltage VR. The input emitter-follower circuit 12 and the current-switch circuit 13 form the ECL receiver mentioned hereinbefore. The ECL receiver referenced 11A is biased between the first and the second supply voltages Vcc (typically the ground) and Vee (e.g. -4.5 V for the 100 K ECL family). The role of ECL receiver 11A is to amplify the input signal Vin. The amplified signals VA and VB are respectively available at nodes A and B of the ECL receiver. The active pull-down circuit 14 is comprised of two emitter-follower circuits each consisting of a bipolar NPN transistor and a terminal impedance consisting of a NFET as the emitter load. These devices are referenced Q5, QN1 and Q6, QN2 respectively, for the first and second emitter-follower circuits. The base electrodes of transistors Q5 and Q6 are connected to nodes A and B of the current-switch circuit 13. The active pull-down circuit 14 is connected between said first supply voltage Vcc and a third supply voltage Vt (e.q. Vt=-2 V). First stage 11 supplies two output signals S1 and S2, which drive the second stage.
The second stage 15 includes the ECL-CMOS level-shifter circuit 16 and a booster circuit 17. The latter comprises two NPN bipolar transistors Q7 and Q8 to form the driver output stage of input buffer 10. In the upper part of the level-shifter circuit 16, one pair of PFETs QP1 and QP2 and one pair of NFETs QN3 and QN4 are coupled to drive the base of transistor Q7. PFETs QP1 and QP2 are driven by the signals S1 and S2 supplied by the active pull-down circuit 14. The common node of devices QP2 and QN4 is connected to the base of output transistor Q7. Similarly, the lower part of circuit 16 comprises three NFETs QN5, QN6 and QN7 and one PFET QP3 coupled as shown in FIG. 1. The gate electrode of PFET QP3 is driven by signal S1. The signal supplied by the common node of NFETs QN6 and QN7 drives the base of output transistor Q8. The drain of NFET QN7 and the gate electrode of NFET QN6 are connected to the common node 19 of output transistors Q7 and Q8, referred to as the circuit output node of input buffer 10. When the circuit input signal Vin at the ECL standard is applied to terminal 18 of input buffer 10, the latter produces the MOS/CMOS circuit output signal Vout at terminal 19 which is coupled to the circuit output node.
When the current-switch output signal VA at node A is low (signal VB is high), NFET QN2 cuts off the current of transistor Q6, while transistor Q5 and NFET QN1 are conductive. Thus, active pull-down circuit 14 dissipates only half the power of the conventional ECL-CMOS level-shifter circuit mentioned above.
The circuit buffer 10 of FIG. 1 is of the single phase type because it produces only one phase (Vout) of the circuit output signal. However, should the complement phase (Vout) be required, the second stage 15 must be doubled by a replicate circuit referenced 15', as shown in FIG. 2.
Referring now to FIG. 2, the two-stage input buffer 10 of FIG. 1 is schematically shown in a two-phase version referenced 10' supplying simultaneously Vout and Vout circuit output signals, at terminals 19 and 19'. Input buffer 10 is used to illustrate the various circuits that are necessary for its implementation to establish the component count. The input buffer 10' of FIG. 2 comprises seven circuit blocks and if one excludes the ECL receiver properly said (circuits 12 and 13) and the third supply voltage generator (Vt gen.), the component count is 6 bipolar transistors and 18 FET devices.
In summary, DC current consumed by input buffer 10 is reduced due to the particular active pull-down circuit 14 disclosed therein. In addition, because level-shifter 16 and output driver 17 are combined into a single circuit (ECL-CMOS level-shifter with bipolar booster), input buffer 10 is only formed by two stages instead of three as in comparative circuits. Consequently, higher speeds and better density integration are achieved with respect to said input buffer 10. For example, there is claimed a propagation delay time less than 1,8 ns at 10-mW power dissipation. However, the input buffer 10 of FIG. 1 still has some major inconveniences, because it provides only a partial solution to the problems mentioned above as will be explained hereinafter.
First, active pull-down circuit 14 still dissipates excessive power, even though less than in prior art circuits because in the quiescent state, either transistor Q5 or Q6 is conductive. Thus, current is drawn from the supply voltage Vcc. In addition, pull-down circuit 14 necessitates a specific Vt reference voltage generator (apparent from FIG. 2) which needs several components for its implementation. Input buffer 10 is a relatively dense circuit, (since it has a two-stage structure, when compared with prior art three-stage input buffers) but, in the two-phase version of FIG. 2, the necessary replication of the second stage 15, significantly reduces the advantages claimed in the single phase version in terms of integration density.
Moreover, the input buffer 10 of FIG. 1 is relatively slow, because of the two-level structure of the lower part of level-shifter circuit 16, which slows down the control of output transistor Q8. Finally, because the active pull-down circuit 14 shifts the first stage output signals S1 and S2 by only one Vbe (base-emitter voltage drop of transistor Q5 or Q6, around 0,8V), only a low amplification effect is produced. As a result, more devices are required in the level-shifter circuit 16.